-------------------------------------------------------------------------------- -------------------------------------------------------------------------------- Introduction: "Von Neumann" is a CPU inspired by and designed with Tanenbaum's "Structured Computer Organization" in mind, and it has been used to teach CPU design principles at D'Youville College for the past three years. It was written during the 4th edition of Tanenbaum's text before the author added Richard Salter's Java simulator of the Mic1 in the 5th edition. Nonetheless "Von Neumann" incorporates different design principles and a different microcode than the Mic1. Also, "Von Neumann" runs using tkgate which make varying the circuitry or the microcode convenient, and therefore ideal for teaching. -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- Quick Start: For the impatient, first make sure you have tkgate installed. Fire it up and read in VonNeumann.v. Press the "Start Simulation" button (it looks like an oscillascope). The buttons on the tool bar will change and the "Load Memory" button will appear. Press it and load VonNeumann.mem. Advance the time a bit by pressing the "Step" button and then flip the "rst" switch on the CPU itself to the "on" position to reset all the registers to zero --- as long as the "rst" switch is "on" the registers will remain zeroed. Flipping it to the "off" position will allow the execution to proceed. You can then watch the cpu evolves as the program is executed. -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- Design: "Von Neumann" features seven 8-bit registers which can write onto two buses, the A and B bus, and can read from one bus, the C bus. The A and B buses are inputs to the ALU and the C bus carries the result back to the registers. The ALU features 16 airthmetic and logic operations ... see below. The memory for "Von Neumann" is divided into two seperate chips: a DATA RAM and a TEXT ROM. The TEXT ROM contains the ISA instructions of the program to be run and the DATA RAM contains the data on whch program will act. The DATA RAM itself is divided into two regions: memory locations for the LV and for the STACK. (The division between these two regions is set by a switch in the CPU.) The seven registers have the following purposes: MDR = "memory data register" which reads/writes data to the DATA RAM MAR = "memory address register" which addresses the DATA RAM MBR = "memory buffer register" which reads from the TEXT ROM PC = "program counter" which addresses the TEXT ROM TOS = "top of stack" which contains the value of the top of the stack SP = "stack pointer" which contains the address of the top of the stack H = a scratch register The Microcode ROM is 32-bits wide 7:0 = NEXT_ADDR 10:8 = write to A bus 001 = H writes to A 010 = TOS writes to A 011 = SP writes to A 100 = MBR writes to A 101 = PC writes to A 110 = MAR writes to A 111 = MDR writes to A 13:11 = like 10:8, but write to B bus 21:14 = read from C bus bit 14 = H reads from C bit 15 = TOS reads from C bit 16 = SP reads from C bit 17 = MBR reads from TEXT ROM bit 18 = PC reads from C bit 19 = MAR reads from C bit 20 = MDR reads from C or DATA RAM bit 21 = 0 - MDR reads from C 1 - MDR reads from DATA RAM 22 = MDR writes to DATA RAM 26:23 = ALU 0000 = A + B 0001 = A and B 0010 = A or B 0011 = INC A 0100 = INC B 0101 = DEC A 0110 = DEC B 0111 = A<< 1000 = B<< 1001 = A * B 1010 = A div B 1011 = A mod B 1100 = A xor B 1101 = not A 1110 = not B 1111 = B - A 28:27 = UNUSED 30:29 = Branch JMP 00 = NEXT_ADDR 01 = Branch to MBR 10 = Branch to ADDR_1 11 = Branch to ADDR_2 31 = 0 - MAR points to LV 1 = MAR points to stack -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- The ISA: HEX Assembly 00 NOP: No operation 01 MAIN: Increment to the next ISA command 02 PUSH + DATA_LV_ADDR : Push a value from LV to STACK in DATA RAM (DATA_LV_ADDR = address in LV from where value is copied) 03 POP: Pop a value from the STACK and discard 04 ADD: Pop the top two values from STACK, add them and then PUSH the answer to STACK 05 STORE + DATA_LV_ADDR : Pop value from STACK and place in LV (DATA_LV_ADDR = address in LV where value is stored) 06 GOTO + TEXT_ADDR : Jump to address TEXT_ADDR for the instruction 07 IFZ - This instruction is incomplete - GOTO if the Z flag is high Z=1 if the result from the ALU is zero, Z=0 otherwise -------------------------------------------------------------------------------- NOP: Pseudo-Microcode: - Binary: Address Bits 31:0 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 Hex: Address Hex 00 00 00 00 01 -------------------- MAIN: Pseudo Microcode: PC = PC + 1 ; read MBR from TEXT Branch on MBR Binary: Address Bits 31:0 0000 0001 0000 0001 1000 0110 0000 0101 0001 0000 0001 0000 0010 0000 0000 0000 0000 0000 0000 0000 Hex: Address Hex 01 01 86 05 10 10 20 00 00 00 -------------------- PUSH: Pseudo Microcode: PC = PC + 1 ; read MBR from TEXT MAR = MBR MAR = SP = SP + 1 ; read MDR from DATA/LV TOS = MDR ; write MDR to DATA/STACK Goto MAIN Binary: Address Bits 31:0 0000 0010 0000 0001 1000 0110 0000 0101 0001 0001 0001 0001 0000 0000 0000 1000 0000 0100 0001 0010 0001 0010 0000 0001 1011 1001 0000 0011 0001 0011 0001 0011 1000 0000 0100 0000 1000 0111 0001 0100 0001 0100 0000 0000 0000 0000 0000 0000 0000 0001 Hex: Address Hex 02 01 86 05 11 11 00 08 04 12 12 01 B9 03 13 13 80 40 87 14 14 00 00 00 01 -------------------- POP: Pseudo Microcode: MAR = SP = SP - 1 Read MDR from DATA/STACK TOS = MDR ; Goto MAIN Binary: Address Bits 31:0 0000 0011 0000 0010 1000 1001 0000 0011 0001 0101 0001 0101 1000 0000 0011 0000 0000 0000 0001 0110 0001 0110 0000 0000 0000 0000 1000 0111 0000 0001 Hex: Address Hex 03 02 89 03 15 15 80 30 00 16 16 00 00 87 01 -------------------- ADD: Pseudo Microcode: MAR = SP = SP - 1 H = TOS ; Read MDR from DATA/STACK MDR = TOS = MDR + H Write MDR to DATA/STACK ; Goto MAIN Binary: Address Bits 31:0 0000 0100 0000 0010 1000 1001 0000 0011 0001 0111 0001 0111 1000 0000 0011 0000 0100 0010 0001 1000 0001 1000 0000 0000 0001 0000 1000 1111 0001 1001 0001 1001 1000 0000 0100 0000 0000 0000 0000 0001 Hex: Address Hex 04 02 89 03 17 17 80 30 42 18 18 00 10 8F 19 19 80 40 00 01 -------------------- STORE: Pseudo Microcode: PC = PC + 1 ; Read MBR from TEXT MAR = MBR MDR = TOS ; Write MDR to DATA/LV MAR = SP = SP - 1 Read MDR from DATA/STACK TOS = MDR ; Goto MAIN Binary: Address Bits 31:0 0000 0101 0000 0001 1000 0110 0000 0101 0001 1010 0001 1010 0000 0000 0000 1000 0000 0100 0001 1011 0001 1011 0000 0000 0101 0000 0000 0010 0001 1100 0001 1100 0000 0010 1000 1001 0000 0011 0001 1101 0001 1101 1000 0000 0011 0000 0000 0000 0001 1110 0001 1110 0000 0000 0001 0000 0000 0010 0000 0001 Hex: Address Hex 05 01 86 05 1A 1A 00 08 04 1B 1B 00 50 02 1C 1C 02 89 03 1D 1D 80 30 00 1E 1E 00 10 02 01 -------------------- GOTO: Pseudo Microcode: Read MBR from TEXT PC = MBR ; Goto MAIN Binary: Address Bits 31:0 0000 0110 0000 0000 0000 0010 0000 0000 0001 1111 0001 1111 0000 0000 0000 0100 0000 0100 0000 0001 Hex: Address Hex 06 00 02 00 1F 1F 00 04 04 01 -------------------- IFZ: Pseudo Microcode: MAR = SP = SP - 1 H = TOS ; Read MDR from DATA/STACK TOS = MDR PC = PC + 1 ; Read MBR from TEXT IF(Z=0) Branch ADDR_1 Binary: Address Bits 31:0 0000 0111 0000 0010 1000 1001 0000 0011 0010 0000 0010 0000 1000 0000 0011 0000 0100 0010 0010 0001 0010 0001 0000 0000 0000 0000 1000 0111 0010 0010 0010 0010 0000 0001 1000 0110 0000 0101 0010 0011 0010 0011 0100 0000 0000 0000 0000 0001 0000 0001 Hex: Address Bits 31:0 07 02 89 03 20 20 80 30 42 21 21 00 00 87 22 22 01 86 05 23 23 40 00 01 01 -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- Example Code in ISA - Fibonacci TEXT ROM: Assembly HEX TEXT_ADDR VALUE LOOP: PUSH 00 02 i 01 00 PUSH 02 02 j 03 01 ADD 04 04 PUSH 05 02 j 06 01 STORE 07 05 i 08 00 STORE 09 05 j 1A 01 GOTO 1B 06 LOOP 1C 00 DATA RAM: DATA_LV_ADDR VALUE 00 00 01 01 02 anything SYMBOL TABLE: SYMBOL DATA_LV_ADDR i 00 j 01 k 02